The constant battle for power-efficient computing

Speaker: George Michelogiannakis , LBNL

Date: Wednesday, December 04, 2013

Time: 2:30 PM to 4:00 PM Note: all times are in the Eastern Time Zone

Refreshments: 2:15 PM

Public: Yes

Location: 32-G882

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Host: Professor Daniel Sanchez, CSG - CSAIL - MIT

Contact: Sally O. Lee, 3-6837, sally@csail.mit.edu

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Reminders to: seminars@csail.mit.edu

Reminder Subject: TALK: The constant battle for power-efficient computing

Recent technology scaling has led to the realization that communication, and not computation, dominates energy costs. This realization, coupled with the constant increase of parallelism and the fact that power consumption is typically the primary design constraint, results in increased difficulty in providing sufficient communication bandwidth to keep processors busy. Power is a critical challenge for HPC, datacenters and consumer electronics. In HPC, a 1000x improvement is performance is needed with only a 10x increase in power by 2018. Moreover, datacenters require $7B just for cooling in the USA, which is projected to increase by four times in the near future. Finally, consumer electronics require a 2x increase in performance with no increase in power every two years to remain competitive.
In this talk, I will present a my work that addresses efficient data movement on and off chips, and DRAM access. I will focus on collective memory transfers, which maximize DRAM performance and minimize power in stencil computations by guaranteeing in-order access patterns. I will also focus on the channel reservation protocol, which eliminates congestion in system-wide networks in order to increase throughput and reduce latency for benign traffic, and therefore increase the utilization of costly network bandwidth.

Bio:

George Michelogiannakis is currently a postdoctoral research fellow at the Lawrence Berkeley National Laboratory. He is part of the computer architecture laboratory which examines key computer architecture research challenges both on and off chip. He completed his PhD at Stanford University in 2012 with Prof. William J. Dally. His past work focuses on on-chip network with numerous contributions to flow control, congestion, allocation, and co-design with chip multiprocessors. His other work includes congestion control for system-wide networks, precision loss avoidance for system-wide reduction operations, and maximizing DRAM efficiency by taking advantage of advanced language constructs. George Michelogiannakis was the recipient of the Stanford Graduate Fellowship, and numerous other awards during his previous studies.

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Created by Sally O. Lee at Tuesday, November 19, 2013 at 1:24 PM.