Efficiently Exploiting Low-Activity Factors to Accelerate RTL Simulation
, UC Santa Cruz
Date: Monday, November 30, 2020
Time: 2:00 PM to 3:00 PM Note: all times are in the Eastern Time Zone
Location: https://mit.zoom.us/meeting/register/tJUrdOqopj8uHdO4gUyVMnfglOFEqIye_Je0 (Registration required, if you haven't registered for this series before)
Event Type: Seminar
Host: Julian Shun, MIT CSAIL
Contact: Julian Shun, email@example.com, firstname.lastname@example.org
Relevant URL: http://fast-code.csail.mit.edu/
Speaker URL: https://scottbeamer.net/
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TALK: Efficiently Exploiting Low-Activity Factors to Accelerate RTL Simulation
Simulation is a critical tool for hardware design but its current slow speed often bottlenecks the whole design process. Simulation speed becomes even more crucial for agile and open-source hardware design methodologies, because the designers not only want to iterate on designs quicker, but they may also have less resources with which to simulate them.
Although most signals in a digital design rarely change (low activity factors), most leading simulators still simulate the entirety of the design every cycle. Tracking which signals are unchanged and can thus be reused typically introduces too much overhead to deliver a practical speedup.
In this work, we explore the challenge of efficiently detecting opportunities for reuse, and we demonstrate streamlined techniques to profitably exploit them. Our approach is powered by a novel acyclic graph partitioner which allows us to automate the generation of high-performance simulators. We present ESSENT, a cycle-accurate simulator generator which outperforms both open-source and industrial state-of-the-art simulators on multiple designs. We also use hardware performance counters to investigate how this workload and our optimizations can impact processor frontend bottlenecks.
Scott Beamer is an assistant professor of computer science and engineering at the University of California, Santa Cruz. His research interests include open-source hardware design, high-performance graph processing, and computer architecture. He received the Kaivalya Dixit Distinguished Dissertation Award from SPEC as well as best paper awards from the International Parallel & Distributed Processing Symposium (IPDPS) and the International Symposium on Workload Characterization (IISWC). He has a PhD in Computer Science from the University of California, Berkeley, and was formerly a postdoctoral scholar at Lawrence Berkeley National Laboratory.
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Created by Julian J. Shun at Friday, November 20, 2020 at 10:57 AM.