EECS Special Seminar: Lana Josipović , "High-Level Synthesis of Dynamically Scheduled Circuits"

Speaker: Lana Josipović , EPFL

Date: Thursday, March 11, 2021

Time: 11:00 AM to 12:00 PM Note: all times are in the Eastern Time Zone

Public: No

Location: Virtual - TBD

Event Type: Seminar

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Host: Daniel Sanchez, CSAIL MIT

Contact: Sally O. Lee, 3-6837, sally@csail.mit.edu

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Reminders to: sally@csail.mit.edu

Reminder Subject: TALK: EECS Special Seminar: Lana Josipović , "High-Level Synthesis of Dynamically Scheduled Circuits"

Abstract:
The slowdown in transistor scaling and the end of Moore's law indicate a need to invest in new computing paradigms; specialized hardware devices, such as FPGAs and ASICs, are a promising solution as they can achieve high processing capabilities and energy efficiency. However, a major barrier to the global success of specialized computing is the difficulty of hardware design. High-level synthesis (HLS) tools generate digital hardware designs from high-level programming languages (e.g., C/C++) and promise to liberate designers from low-level hardware description details. Yet, HLS tools are still acceptable only for certain classes of applications and criticized for the difficulty of extracting the desired level of performance: generating good circuits still requires tedious code restructuring and hardware design expertise.
In this talk, I will present a new HLS methodology that produces dynamically scheduled, dataflow circuits out of C/C++ code; the resulting circuits achieve good performance out-of-the-box and realize behaviors that are beyond the capabilities of standard HLS tools. I will describe mathematical models to optimize the performance and area of the resulting circuits, as well as techniques to achieve characteristics that standard HLS cannot support, such as out-of-order memory accesses and speculative execution. These contributions redefine the HLS paradigm by introducing characteristics of modern superscalar processors to hardware designs; such behaviors are key for specialized computing to be successful in new contexts and broader application domains.
Bio:
Lana Josipović completed her PhD at Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland, in 2020. Her research focuses on developing new high-level synthesis (HLS) techniques: the goal is to create hardware designs from high-level programming languages and to enable software developers to build efficient hardware accelerators. During her PhD, Lana interned at Xilinx, where she implemented the ideas of her PhD research into a new compiler targeting next-generation hardware platforms, and Microsoft Research, where she developed new HLS solutions for employing FPGAs in the cloud. She is a recipient of the Google PhD Fellowship in Systems and Networking, Google Women Techmakers Scholarship, Best Paper Award at FPGA'20, and Best Paper Award Nominations at FPGA'18 and CASES'17.

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Created by Sally O. Lee at Friday, February 19, 2021 at 6:10 AM.